This invention relates generally to semiconductor wafer processing and integrated circuit packaging. In particular, the invention relates to bumped semiconductor wafers with wafer-applied underfill, flip chips and flip-chip assemblies, and a method of manufacturing a semiconductor wafer, a flip-chip, or a flip-chip module with a conjoined underfill and solder mask layer.
Assembly of bumped flip chips to printed wiring boards (PWB) and other electronic substrates has become an important pursuit in the microelectronic industry. As more of these components are assembled to form cost-effective electronic modules and flip-chip assemblies, the need increases for an underfill system that obviates the time-consuming sequences required by capillary flow of underfill materials in current assembly processes. Underfill material structurally reinforces the solder bumps, mechanically adheres the flip chip to the PWB, and improves the reliability of the assembly.
Flip chips are formed with ball-shaped beads or bumps of solder affixed to their input/output (I/O) bonding pads. The integrated circuit (IC) flip chip or die may be bonded directly to a packaging substrate, without the need for a separate wirebonded leadframe or for separate I/O connectors such as wires or tapes. During packaging, the chip is xe2x80x9cflippedxe2x80x9d onto its active circuit surface so that the solder balls form electrical connections directly between the bumped chip and conductive traces on a packaging substrate or motherboard.
Underfill materials are typically applied between the surface of the IC and the PWB. In the liquid underfill dispense technique, the underfill is applied at one or more edges of the flip-chip bonded die and capillary action wicks the fluid under the die. During this process, the entire die surface is coated with the underfill. When using highly viscous, no-flow underfills, the underfill may be applied to the PWB prior to die placement. During solder reflow, the underfill liquefies and wets the die site on the PCB and the die surface at the bottom and on the edges of the die.
The capillary flow technology uses underfill encapsulant material of a suitable polymer in the void between the chip and the substrate. The underfill material is typically dispensed around two adjacent sides of the semiconductor chip, with the underfill material flowing by capillary action to fill the gap between the chip and the substrate. Baking or heat treatment then hardens the underfill material. The underfill encapsulant needs to adhere well to the chip and the substrate to improve the solder joint integrity. Underfilling the chip with a subsequently cured encapsulant typically reduces solder joint cracking caused by a thermal expansion mismatch between the chip and the substrate. The cured encapsulant reduces the level of stresses on the solder joints, induced by differential expansion and contraction. An example of an underfill material being applied around the periphery of a flip-chip assembly and partially wicked into the interior region is described by Ralser, et al., in U.S. Pat. No. 6,365,441, xe2x80x9cPartial Underfill for Flip Chip Electronic Packagesxe2x80x9d issued Apr. 2, 2002.
A single layer of underfill encapsulant with an interdispersed flux is described in U.S. Pat. No. 6,194,788, xe2x80x9cFlip Chip with Integrated Flux and Underfillxe2x80x9d by Gilleo et al. issued Feb. 27, 2001. The manufacturing process uses one step to apply a bumped flip chip with the fluxing underfill to a printed circuit, rather than separate fluxing and underfilling steps.
Underfilling methods may use an underfill layer on the die surface and flux applied to a PCB. Yamaji presents an underfill on the surface of a chip and top ends of the bumps, with the flux on the mounting substrate, as described in U.S. Pat. No. 5,925,936, xe2x80x9cSemiconductor Device for Face Down Bonding to a Mounting Substrate and a Method of Manufacturing the Samexe2x80x9d issued Jul. 20, 1999. Capote and others disclose a simplified process for flip-chip attachment to a substrate, which pre-coats the bumped IC chip with an encapsulant underfill material, as described in U.S. Pat. No. 6,121,689, xe2x80x9cSemiconductor Flip-Chip Package and Method for the Fabrication Thereofxe2x80x9d issued Sep. 19, 2000. The encapsulant encases the bumps that extend from contacts on the surface of the chip to the pads of the substrate.
An underfill process using separated flux and underfill that are applied to the die are described by Gilleo, et al., in application WO 99/56312, xe2x80x9cFlip Chip with Integrated Flux, Mask and Underfill,xe2x80x9d published Nov. 4, 1999.
The underfill process often makes the assembly of encapsulated flip-chip printed wire boards (PWB) a time consuming, labor intensive and expensive process with a number of uncertainties. To join the integrated circuit to the substrate, flux generally is placed on the chip or substrate and then the IC is placed on the substrate. The assembly is subjected to a solder reflowing thermal cycle, melting the bumps and soldering the chip to the substrate. The surface tension of the solder aids in the self-alignment of the chip to the substrate pads. Underfill encapsulation of the chip generally follows after reflow.
One of the disadvantages of this encapsulation process is its reduced production efficiency because the underfilling and curing of the encapsulant is a multi-step process, requiring the material to flow through the tiny gap between the chip and the substrate. As chip size increases, the capillary action of the encapsulation procedure becomes even more time-consuming, and is more susceptible to void formation and to the separation of the polymer from the fillers during application. Another general problem is that any flux residue remaining in the gap may reduce the adhesive and cohesive strengths of the underfill-encapsulating adhesive. Furthermore, as the pitch between adjacent bumps decreases, uniform flow of underfill materials becomes increasingly difficult. One solution to this problem is disclosed in U.S. Pat. No. 6,294,840, xe2x80x9cDual-Thickness Solder Mask in Integrated Circuit Package,xe2x80x9d by McCormick, issued Sep. 25, 2001.
In recent research on encapsulation processes, a semiconductor wafer with an array of integrated circuits is coated with underfill material that is approximately the same height as the bumps of a die, before the bumped chips are soldered to a substrate. This thick coating may result in the interference with solder joint formation between the bumps and pads on the electrical substrate. Unfortunately, the close proximity of the underfill to the bump-pad interface can create a physical barrier to consistent, reliable soldering. This approach relies solely on the pre-applied underfill material to fill the gap between the chip and the substrate. The thickness of the underfill-material coating, which is approximately the same height as the bumps of the die, can result in problems during the placement of the die. The thick underfill coating may alter the size and shape of the exposed area of the tops of the solder bumps. These tops may be used as locating features for placement. With coated chips, the exposed area above the bumps is random and the bump diameter may be hard to define, making it difficult to inspect and register the coated parts prior to placement. However, when thinner coatings are used, the volume of pre-applied underfill material is insufficient to fill the gap between the chip and the substrate.
It would be beneficial to have a packaging technology for directly attaching bumped flip chips to an underlying electrical substrate or PWB that allows secure electrical and mechanical die attach to the PWB, while eliminating the need for time-consuming dispensing operations for dispensing underfill materials around attached flip chips, as required by current capillary-flow underfill methods. The packaging technology would allow the flip chips to be bonded effectively to a substrate, with highly reliable electrical interconnections and protective underfill material for secure die bonding, stress relief for the bumps and effective environmental protection. Furthermore, the technology would not require pre-coating material up to the top of the solder bumps, would eliminate bump-recognition challenges, and would eliminate an additional tack step typically needed to maintain alignment. Flexibility to apply an optional flux layer before or after bulk epoxy coatings is also desirable.
It would be beneficial, therefore, to provide an improved method for attaching a flip chip to an electrical substrate and a process for applying underfill at the chip or wafer level, which provide above-mentioned improvements and overcome the deficiencies and obstacles described above.
One aspect of the invention provides a method for attaching a flip chip to an electrical substrate. A bumped flip chip is provided that includes an active surface and a plurality of connective bumps extending from the active surface, each connective bump including a side region. A thin layer of an underfill material is applied to the active surface of the flip chip and to a portion of the side regions of the connective bumps. The flip chip is positioned on the electrical substrate that includes a thick layer of a solder mask disposed on the electrical substrate. The flip chip is heated to electrically connect the flip chip to the electrical substrate, wherein the underfill material and the solder mask combine to form a stress-relief layer when the flip chip is electrically connected to the electrical substrate.
Another aspect of the invention provides a flip-chip assembly. The flip-chip assembly comprises a bumped flip chip with an active surface and a plurality of connective bumps extending from the active surface. A thin layer of an underfill material is disposed on the active surface of the flip chip and on a portion of a side region of the connective bumps. The bumped flip chip is electrically connected to an electrical substrate that includes a thick layer of a solder mask, the solder mask and the underfill material combining to form a stress-relief layer.
Another aspect of the invention provides a wafer-applied underfill process. A bumped semiconductor wafer including an active surface and a plurality of connective bumps extending from the active surface is provided. An underfill material is applied to the active surface of the semiconductor wafer and a portion of a side region of the connective bumps, wherein the underfill material extends from the active surface to a thickness between nominally 20 percent and 60 percent of a connective bump height. The underfill material is heated to flow around the connective bumps.
The present invention is illustrated by the accompanying drawings of various embodiments and the detailed description given below. The drawings should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof. The foregoing aspects and other attendant advantages of the present invention will become more readily appreciated by the detailed description taken in conjunction with the accompanying drawings.